Reference is made FIG. 1 showing a conventional non-volatile static random access memory (NVSRAM) cell 10. The cell 10 includes a first electrically erasable programmable read only (EEPROM) memory string 12 formed by a floating gate transistor 14 connected in series with a select transistor 16 between a first supply voltage node 18a and a first latch node 20. The cell 10 further includes a second EEPROM memory string 22 formed by a floating gate transistor 24 connected in series with a select transistor 26 between the first supply voltage node 18a and a second latch node 30. The control gates of the floating gate transistors 14 and 24 are connected to a control gate line 32 which is driven by a control gate signal (CG). The control gates of the select transistors 16 and 26 are connected to a reload line 34 which is driven by a reload signal (Reload). The cell 10 further includes a flip-flop circuit formed by a static random access memory cell 40 of the well-known 6T-type including a latch circuit 42 formed by cross-coupled inverter circuits 44 and 46. Inverter circuit 44 is formed by a first p-channel transistor 48 coupled in series with a first n-channel transistor 50 between the second supply voltage node 18 and a third supply voltage node 19. The series connection of the drain terminals of transistors 48 and 50 is made at the first latch node 20. Inverter circuit 46 is formed by a second p-channel transistor 52 coupled in series with a second n-channel transistor 54 between the second supply voltage node 18 and third supply voltage node 19. The series connection of the drain terminals of transistors 52 and 54 is made at the second latch node 30. The control gates of the transistors in the inverter circuit 44 are coupled to the second latch node 30, and the control gates of the inverter circuit 46 are coupled to the first latch node 20. The first and second latch nodes 20 and 30, respectively, store complementary data states. A first access transistor 60 is coupled between the first latch node 20 and a first data line 62. A second access transistor 64 is coupled between the second latch node 30 and a second data line 66. The first and second data lines 62 and 66, respectively, carry complementary data states during read and write operations. The control gates of the access transistors 60 and 64 are connected to a word line 68 which is driven by a word line signal (WL).
Operation of this circuit for writing data into and reading data from the memory cell is well known in the art. The normal loading of non-volatile data into the SRAM is as follows:
The nonvolatile EEPROM cells are put in a read condition. Node 18a is set at low level, like node 19, and the CG line is put at a reference level (typically the thresholds of a virgin cell of 0.5V to 1V). The WL is set at low level. The Reload line is set at high level. A voltage ramp is then applied to the supply node 18 of the flip-flop. Each terminal of the flip-flop is connected to EEPROM cells in a different conduction state (differential, one erased, one programmed). The programmed cell at least draws more current than the erased cell (which in principle draws no current). This un-balances the flip-flop, which during its power up phase will be set to low at the side connected to the programmed cell.
An alternate activation mode consists in pulling high node 18a during the power up of the flip-flop. Then, the side of the flip-flop connected to the programmed cell will go high. Either activation mode (node 18a low or high) has known advantages and disadvantages.
The load process controlled by the supply of the flip-flop requires switching a power supply or controlling a voltage ramp on it, and the switching process will start when the supply of the flip-flop reaches the thresholds of the transistors in the flip-flop, based on the differential conduction of the EEPROM cells.
A memory array 80 as shown in FIG. 2 is formed by a plurality of cells 10 arranged in a matrix including a plurality of rows and columns. The first and second data lines 62 and 66 are shared by cells 10 in each column and are connected to sensing circuitry 82 and a write circuit 84. The word line 68 is shared by cells 10 in each row and is connected to a word line decoder circuit 86. The control gate line 32 and reload line 34 are shared by cells 10 in each row and are connected to a control circuit 88. In alternative embodiments, the lines 32 and 34 can be global lines that are shared across the entire array.
There is a need in the art for an improved memory cell structure.